SDK system based on Makefiles

[lgpl/argeo-commons.git] / org.argeo.api.uuid / Makefile

diff --git a/org.argeo.api.uuid/Makefile b/org.argeo.api.uuid/Makefile
index 093701fbd14fd5348e4e4ea35129c15003807ec0..3feb61027a6d45d5e55e3b3133ebf6c7d393fff8 100644 (file)
--- a/org.argeo.api.uuid/Makefile
+++ b/org.argeo.api.uuid/Makefile
@@ -1,68 +1,23 @@
-include ../sdk.mk
+JNIDIRS = org_argeo_api_uuid
 
-NATIVE_PACKAGE=org_argeo_api_uuid
-TARGET_EXEC := libJava_$(NATIVE_PACKAGE).so
+.PHONY: clean all jni
 
-SRC_DIRS := ./jni/$(NATIVE_PACKAGE)
+all: jni
 
-LDFLAGS=-shared -fPIC -Wl,-soname,$(TARGET_EXEC).$(MAJOR).$(MINOR)
-
-#
-# Generic Argeo
-#
-BUILD_DIR := ./generated
-META_INF_DIR := ./META-INF
-ARCH := $(shell uname -p)
-
-# Every folder in ./src will need to be passed to GCC so that it can find header files
-INC_DIRS := $(shell find $(SRC_DIRS) -type d) /usr/lib/jvm/java/include /usr/lib/jvm/java/include/linux
-
-.PHONY: clean all ide
-all: $(BUILD_DIR)/$(TARGET_EXEC)
-
-ide: $(META_INF_DIR)/$(ARCH)/$(TARGET_EXEC)
-
-$(META_INF_DIR)/$(ARCH)/$(TARGET_EXEC): $(BUILD_DIR)/$(TARGET_EXEC)
-       mkdir -p $(dir $@)
-       cp $(BUILD_DIR)/$(TARGET_EXEC) $(dir $@)
-
-# Find all the C and C++ files we want to compile
-# Note the single quotes around the * expressions. Make will incorrectly expand these otherwise.
-SRCS := $(shell find $(SRC_DIRS) -name '*.cpp' -or -name '*.c' -or -name '*.s')
-
-# String substitution for every C/C++ file.
-# As an example, hello.cpp turns into ./build/hello.cpp.o
-OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
-
-# String substitution (suffix version without %).
-# As an example, ./build/hello.cpp.o turns into ./build/hello.cpp.d
-DEPS := $(OBJS:.o=.d)
-
-# Add a prefix to INC_DIRS. So moduleA would become -ImoduleA. GCC understands this -I flag
-INC_FLAGS := $(addprefix -I,$(INC_DIRS))
-
-# The -MMD and -MP flags together generate Makefiles for us!
-# These files will have .d instead of .o as the output.
-CPPFLAGS := $(INC_FLAGS) -MMD -MP
-
-# The final build step.
-$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
-       $(CC) $(OBJS) -o $@ $(LDFLAGS)
-
-# Build step for C source
-$(BUILD_DIR)/%.c.o: %.c
-       mkdir -p $(dir $@)
-       $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
+jni:
+       $(foreach dir, jni/$(JNIDIRS), $(MAKE) -C $(dir);)
+       
+clean:
+       $(foreach dir, jni/$(JNIDIRS), $(MAKE) -C $(dir) clean;)
 
-# Build step for C++ source
-$(BUILD_DIR)/%.cpp.o: %.cpp
-       mkdir -p $(dir $@)
-       $(CXX) $(CPPFLAGS) $(CXXFLAGS) -c $< -o $@
+#ide: $(META_INF_DIR)/$(ARCH)/$(TARGET_EXEC)
+       
+#$(META_INF_DIR)/$(ARCH)/$(TARGET_EXEC): $(BUILD_DIR)/$(TARGET_EXEC)
+#      mkdir -p $(dir $@)
+#      cp $(BUILD_DIR)/$(TARGET_EXEC) $(dir $@)
 
-clean:
-       rm -r $(BUILD_DIR)
 
-# Include the .d makefiles. The - at the front suppresses the errors of missing
-# Makefiles. Initially, all the .d files will be missing, and we don't want those
-# errors to show up.
--include $(DEPS)
\ No newline at end of file
+%:
+       @echo Making '$@' $(if $^,from '$^')
+       @echo 'OBJ=$(OBJ)'
+       @echo 'DEP=$(DEP)'